Abstract

Although an agile approach is standard for software design, how to properly adapt this method to hardware is still an open question. This work addresses this question while building a system on chip (SoC) with specialized accelerators. Rather than using a traditional waterfall design flow, which starts by studying the application to be accelerated, we begin by constructing a complete flow from an application expressed in a high-level domain-specific language (DSL), in our case Halide, to a generic coarse-grained reconfigurable array (CGRA). As our understanding of the application grows, the CGRA design evolves, and we have developed a suite of tools that tune application code, the compiler, and the CGRA to increase the efficiency of the resulting implementation. To meet our continued need to update parts of the system while maintaining the end-to-end flow, we have created DSL-based hardware generators that not only provide the Verilog needed for the implementation of the CGRA, but also create the collateral that the compiler/mapper/place and route system needs to configure its operation. This work provides a systematic approach for desiging and evolving high-performance and energy-efficient hardware-software systems for any application domain.

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BibTeX

@article{bahr2020,
  title={Creating an Agile Hardware Design Flow},
  author={Rick Bahr and Clark Barrett and Nikhil Bhagdikar and Alex Carsello and Ross Daly and Caleb Donovick and David Durst and Kayvon Fatahalian and Kathleen Feng and Pat Hanrahan and Teguh Hofstee and Mark Horowitz and Dillon Huff and Fredrik Kjolstad and Taeyoung Kong and Qiaoyi Liu and Makai Mann and Jackson Melchert and Ankita Nayak and Aina Niemetz and Gedeon Nyengele and Priyanka Raina and Stephen Richardson and Raj Setaluri and Jeff Setter and Kavya Sreedhar and Maxwell Strange and James Thomas and Christopher Torng and Leonard Truong and Nestan Tsiskaridze and Keyi Zhang},
  journal={Design Automation Conference (DAC)},
  year={2020},
  month={July}
}